A read access from a small signal, differential memory, e.g., a static random access memory (SRAM), generally comprises three operations. A first operation, known as or referred to as “development,” applies a voltage differential on the sense nodes of a sense amplifier. A second operation, known as or referred to as “evaluate,” amplifies a small voltage differential on the sense nodes into a full swing, e.g., “rail to rail,” signal to determine the value of the memory cell. A third operation, known as or referred to as “pre-charge,” charges the sense nodes so that they are ready for a subsequent access.
Often, under the conventional art, the development and evaluate operations are timed using a “replica,” e.g., delay, circuit. A replica circuit generally comprises a bit line with the same load as the functional bit lines, with the circuit designed so that it always discharges. This replica can be in addition to, or instead of, a delay chain, e.g., of inverters. The replica is not used to store data; rather, it is used to track various delays of a memory circuit. Because the replica circuit is formed on the same die as the memory circuits, there is a degree of correspondence between the analog characteristics, e.g., capacitance, threshold voltage, static and dynamic leakage, switching rate and the like, of a replica and “real” memory circuits. For example, a replica circuit may track changes in operating conditions, e.g., Vdd and/or operating temperature, as well as global changes in process variation.
Unfortunately, the replica circuit and the real memory circuits are not identical. For example, a replica circuit generally does not track local process variations, e.g., statistical variations in dopant density, that may cause timing differences between a replica and “real” memory circuits, causing differences in behavior between them. Consequently, a replica timer is usually designed to be slower than a mirrored memory circuit. In addition, there is usually some variation among memory cells and sense amplifiers within a memory array. Accordingly, a replica timer must be designed to leave timing margin to allow for the slowest memory cells and sense amplifiers to complete their operations. The accumulation of timing margins to allow for worst case differences between replicas and actual memory, and to allow for the slowest memory cells and sense amplifiers, typically results in memory accesses, e.g., reads and/or writes, which occur slower than necessary, for most memory cells.
An alternative to a replica circuit is to use a separate clock phase for each operation, e.g., one phase for development, one phase for evaluate and one phase for precharge. Thus three clock phases, one and one half clock cycles, are required to complete all three operations. In addition, conventional-art phase-based designs typically add an extra clock phase to align the memory operations with the same clock phase, e.g., a rising edge. Accordingly, the conventional art typically utilizes four clock phases, two clock cycles, to complete the three operations, further slowing memory throughput under the conventional art.